Semiconductor device and method of fabricating same

ABSTRACT

There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (V th ) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method offabricating the same. More particularly, the invention relates to adevice structure for reducing variations in threshold voltage V_(th) ofa power semiconductor device having an MOS gate with time to stabilizeelectrical characteristics, and a method of fabricating the same.

2. Description of the Background Art

FIG. 19 is a fragmentary plan view of a power insulated gate bipolartransistor (referred to hereinafter as an IGBT) as an example of theconventional semiconductor devices. FIG. 20 is a cross-sectional viewtaken along the line XX—XX of FIG. 19.

In FIGS. 19 and 20, the reference numeral 1 designates a P⁺ substrate; 2designates an N⁺ layer; 3 designates an N⁻ layer; and 4 designates asemiconductor body comprised of the P⁺ substrate 1 the N⁺ layer 2 andthe N⁻ layer 3.

The reference numeral 5 designates a P⁺ base layer; 6 designates an N⁺emitter layer; 7 designates a gate insulating film made of siliconoxide; 8 designates a gate electrode of polysilicon; 9 designates a gateinterconnection line of Al; 10 designates an emitter electrode; 11designates guard rings; 12 designates a passivation film for isolationbetween the gate electrode 8 and the emitter electrode 10; 13 designatesan emitter wire bonding region; 14 designates a surface protective filmof silicon nitride for covering the IGBT surface except the emitterwiring bonding region 13 and a gate bonding pad (not shown) which is apart of the gate interconnection line 8 9; 15 designates a channelstopper; 16 designates a silicon oxide film; 17 designates a polysiliconfilm; 18 designates a passivation film; and 19 designates a collectorelectrode.

FIG. 21 is a flow chart of the fabrication process of the conventionalIGBT.

Referring to FIG. 21, the semiconductor body 4 is initially formed, andthe P⁺ base layer 5, and P wells, P⁺ layers serving as the guard rings11 are formed in the surface of the N⁻ layer 3 of the semiconductor body4. The gate insulating film 7 of silicon oxide is formed on the surfaceof the P⁺ base layer 5, and a polysilicon film is formed on the surfaceof the gate insulating film 7. Then the N⁺ emitter layer 6 and thechannel stopper 15 are formed by diffusion, and the passivation films 12and 17 18 are formed. The gate interconnection line 9 and the emitterelectrode 10 are formed as Al electrodes. Thereafter, the surfaceprotective film 14 is formed to cover the IGBT surface except theemitter wire bonding region 13 and the gate bonding pad which is a partof the gate interconnection line 9. A silicon nitride film serving asthe surface protective film 14 is formed by plasma CVD process (referredto hereinafter as P-CVD process) at a temperature of about 300 to 400°C. in an atmosphere of a mixed silane-ammonia gas. Then the IGBT isexposed to radiation for lifetime control thereof and is subjected toheat treatment at a temperature of 300 to 400° C. to eliminatedistortion resulting from the radiation.

The surface protective film 14 is formed for the following purposes: (1)to prevent shorting of the emitter electrode 10 and gate interconnectionline due to mechanical scratches, (2) to prevent shorting of an aluminumelectrode (not shown) formed on the guard rings 11 in a peripheral areaof a chip due to external contamination, and (3) to prevent moisturefrom corroding aluminum thin wires of The device.

In the past, oxide films formed by the low pressure CVD process(referred to hereinafter as LP-CVD process), such as phospho-silicateglass (PSG), have been used as the surface protective film of the IGBT.However, silicon nitride films formed by the P-CVD process have recentlybeen used as the surface protective film since the material of thesilicon nitride films is more air-tight and mechanically stronger as asurface protective film than that of the PSG films. In this manner, theconventional IGBT is constructed as above described using the siliconnitride film formed by the P-CVD process as the surface protective filmand is fabricated through the above-mentioned fabrication process.

To evaluate the long-term stability of electrical characteristics of theIGBT, a HTGB test (high temperature gate bias test) was performed. TheHTGB test is to continuously apply a gate signal V_(GES)≈+20 V or −20 Vbetween the gate and emitter, with the emitter and collector grounded,at an atmospheric temperature T_(a)=125° C. to determine the relationbetween a V_(GES) voltage application time and variations in thresholdvoltage V_(th) with time.

FIG. 22 is a graph of the result of the HTGB test made on theconventional semiconductor devices.

The test conditions in FIG. 22 are an atmospheric temperature Ta≈125° C.and V_(GES)=±20 V for an IGBT, and an atmospheric temperature Ta=150° C.and V_(GES)=−30 V for an MOSFET. Variations in threshold voltage V_(th)is represented by the percentage of V_(th) variations.

The MOSFET used herein is constructed such that the P⁺ substrate isremoved from the structure of FIG. 20 and the N⁺ layer 2 is replacedwith an N⁺ substrate. The fabrication process of the MOSFET does notinclude the radiation and the heat treatment for distortion eliminationof FIG. 21.

Referring to FIG. 22, for the IGBT, with V_(GES)=+20 V applied, theV_(th) variation percentage is several percent which presents noparticular problems in terms of long-term stability of the electricalcharacteristics. For the IGBT, with V_(GES)=−20 V applied, V_(th)decreases with the passage of the V_(GES) application time, and theV_(th) variation percentage exceeds 10% after an elapse of 1000 hours.In addition, the V_(th) variation does not tend to become saturated over1000 hours. Thus, the conventional IGBT has been disadvantageous inlong-term stability of the electrical characteristics.

For the conventional MOSFET, with V_(GES)=−30 V applied, V_(th)decreases with the passage of the V_(GES) application time and tends tobecome saturated after an elapse of 500 hours, as compared with theIGBT. However, the MOSFET exhibits the V_(th) variation percentagereaching 10%. Thus, the conventional MOSFET has been disadvantageous inlong-term stability of the electrical characteristics.

The application of a negative voltage V_(GES) varies the thresholdvoltage V_(th) which in turn is slow in becoming saturated, possibly forthe reasons to be described below.

The silicon nitride film formed by the P-CVD process contains a largeamount of hydrogen atoms. For example, the number of Si—H chemical bondsin the silicon nitride film formed by the P-CVD process is 1.0×10²²cm^(—3) to 1.6×10²² cm⁻³ by measurement using FT-IR (Fourier transforminfrared spectroscopy) technique. The number of Si—H chemical bonds inthe PSG film is on the order of 0.4×10²² cm⁻³. The hydrogen atoms in thesilicon nitride film readily migrate through the surface protective film14 of silicon nitride, the aluminum electrodes such as the gateinterconnection line 9 and emitter electrode 10, the passivation film 1712 and the gate insulating film 7 of silicon oxide depending upon theatmospheric temperatures and the polarity and magnitude of the appliedvoltage to reach a silicon-silicon oxide interface at the surface of thesemiconductor body 4 without difficulty. Dangling bonds at thesilicon-silicon oxide interface are bonded to hydrogen atoms from thesilicon nitride film to form Si—H chemical bonds at the silicon-siliconoxide interface, resulting in an unstable interface state. It takes timeto stabilize the interface state, which is considered to cause thedifficulty in saturating the varying threshold voltage V_(th).

One of the reasons why such a problem is not encountered for theconventional PSG film is considered to be the fact that the PSG filmcontains fewer Si—H chemical bonds and, accordingly, fewer hydrogenatoms than the silicon nitride film formed by the P-CVD process.

Further, the radiation for lifetime control of the IGBT increases thedefects at the silicon-silicon oxide interface to accelerate theformation of Si—H bonds at the silicon-silicon oxide interface, probablyresulting in increased V_(th) variations with time.

SUMMARY OF THE INVENTION

According to the present invention, a semiconductor device comprises: afirst semiconductor layer of a first conductivity type having first andsecond major surfaces; a first semiconductor region of a secondconductivity type formed selectively in the first major surface of thefirst semiconductor layer so that the first semiconductor layer isexposed in a peripheral portion of the first major surface and the firstsemiconductor layer is exposed in the form of insular regions in acentral portion of the first major surface; a second semiconductorregion of the first conductivity type formed in a surface of the firstsemiconductor region, with channel regions provided between the secondsemiconductor region and the insular regions of the first semiconductorlayer; a gate insulating film formed on a surface of the channelregions; a gate formed on the gate insulating film; a first mainelectrode formed over a surface of the gate, with an interlayerinsulating film therebetween, for covering a surface of the secondsemiconductor region and electrically connected to the secondsemiconductor region, the first main electrode having an end extendingto a boundary between the peripheral portion of the first major surfaceand the central portion thereof; a second main electrode formed on thesecond major surface of the first semiconductor layer; and an integralsurface protective film for covering at least the peripheral portion ofthe first major surface other than the central portion of the firstmajor surface.

In the semiconductor device of the present invention, the surfaceprotective film is formed only in the peripheral area of the device, notin the device area including the channels, to reduce the amount ofhydrogen atoms migrating to the silicon-silicon oxide interface in thecell area, enhancing the electrical stability of the semiconductordevice.

Preferably, the semiconductor device further comprises: a gateinterconnection line formed selectively on the surface of the gate,wherein the first main electrode is not formed on the surface of thegate on which the gate interconnection line is formed, and wherein atrench is formed between the first main electrode and the gateinterconnection line for electrical isolation therebetween.

The provision of the gate interconnection line stabilizes the gatepotential and the cell switching operation of the semiconductor device.

Preferably, the surface protective film extends from a surface of thegate interconnection line through the trench to the surface of the firstmain electrode.

The provision of the surface protective film covering the trenchelectrically isolating the gate interconnection line and the first mainelectrode from each other prevents shorting of the gate interconnectionline and the first main electrode, increasing a product yield.

According to another aspect of the present invention, a semiconductordevice comprises: a first semiconductor layer of a first conductivitytype having first and second major surfaces; a first semiconductorregion of a second conductivity type formed selectively in the firstmajor surface of the first semiconductor layer so that the firstsemiconductor layer is exposed in a peripheral portion of the firstmajor surface and the first semiconductor layer is exposed in the formof insular regions in a central portion of the first major surface; aplurality of second semiconductor regions of the first conductivity typeformed in a surface of the first semiconductor region, with channelregions provided between the second semiconductor regions and theinsular regions of the first semiconductor layer; a gate insulating filmformed on a surface of the channel regions; a gate formed on the gateinsulating film; a first main electrode formed over a surface of thegate, with an interlayer insulating film therebetween, for coveringsurfaces of the second semiconductor regions and electrically connectedto the second semiconductor regions, the first main electrode having anend extending to a boundary between the peripheral portion of the firstmajor surface and the central portion thereof; a second main electrodeformed on the second major surface of the first semiconductor layer; andan integral surface protective film for covering at least the peripheralportion of the first major surface other than the central portion of thefirst major surface.

In the semiconductor device of the second aspect of the presentinvention, the plurality of cells increases the device capacitance. Thesurface protective film is formed only in the peripheral area of thedevice, not in the device area including the channels, to reduce theamount of hydrogen atoms migrating to the silicon-silicon oxideinterface in the cell area, enhancing the electrical stability of thelarge-capacitance semiconductor device.

Preferably, the surface protective film extends from the peripheralportion of the first major surface to a surface of the first mainelectrode at the end.

Since the gate interconnection line is formed to connect portions of thegate electrode corresponding to the plurality of channels, thesemiconductor device of the present invention provides a stable gatepotential if the entire length of the gate interconnection line mayincrease. This provides a uniform cell switching operation for thelarge-capacitance semiconductor device and a stable operation of thewhole semiconductor device.

Preferably, the semiconductor device further comprises: a gateinterconnection line formed selectively on the surface of the gate,wherein the first main electrode is not formed on the surface of thegate on which the gate interconnection line is formed, and wherein atrench is formed between the first main electrode and the gateinterconnection line for electrical isolation therebetween.

The provision of the surface protective film covering the trenchelectrically isolating the first main electrode and the gateinterconnection line connecting the portions of the gate electrodecorresponding to the plurality of channels from each other preventsshorting of the gate interconnection line and the first main electrodeif the trench for electrically isolating the gate interconnection lineand the first main electrode may be long, increasing the product yieldof the large-capacitance semiconductor device.

Preferably, the semiconductor device further comprises: a secondsemiconductor layer of the second conductivity type formed between saidsecond major surface of said first semiconductor layer and said secondmain electrode.

In the semiconductor device of the present invention, the surfaceprotective film is formed only in the peripheral area of the device, notin the device area including the channels, in an IGBT construction toreduce the amount of hydrogen atoms migrating to the silicon-siliconoxide interface in the cell area, enhancing the electrical stability ofthe semiconductor device of the IGBT construction.

Preferably, the semiconductor device further comprises: a gateinterconnection line formed selectively on the surface of said gate,wherein said first main electrode is not formed on the surface of saidgate on which said gate interconnection line is formed, and wherein atrench is formed between the first main electrode and said gateinterconnection line for electrical isolation therebetween.

The provision of the gate interconnection line in the IGBT constructionstabilizes the gate potential and the cell switching operation of thesemiconductor device of the IGBT construction.

Preferably, said surface protective film extends from a surface of saidgate interconnection line through said trench to the surface of saidfirst main electrode.

The provision of the surface protective film covering the trenchelectrically isolating the gate interconnection line and the first mainelectrode from each other in the IGBT construction prevents shorting ofthe gate interconnection line and the first main electrode, increasingthe product yield of the semiconductor device of the IGBT construction.

Preferably, the semiconductor device further comprises: a secondsemiconductor layer of the second conductivity type formed between thesecond major surface of the first semiconductor layer and the secondmain electrode.

The plurality of cells in the IGBT construction increases the devicecapacitance. The surface protective film is formed only in theperipheral area of the device, not in the device area including thechannels, to reduce the amount of hydrogen atoms migrating to thesilicon-silicon oxide interface in the cell area, enhancing theelectrical stability of the largest-capacitance semiconductor device ofthe IGBT construction.

Preferably, the semiconductor device further comprises: a gateinterconnection line formed selectively on the surface of the gate,wherein the first main electrode is not formed on the surface of thegate on which the gate interconnection line is formed, and wherein atrench is formed between the first main electrode and the gateinterconnection line for electrical isolation therebetween.

Since the gate interconnection line is formed to connect portions of thegate electrode corresponding to the plurality of channels in the IGBTconstruction, the semiconductor device of the present invention providesa stable gate potential if the entire length of the gate interconnectionline may increase. This provides a uniform cell switching operation forthe large-capacitance semiconductor device of the IGBT construction anda stable operation of the whole semiconductor device.

Preferably, the surface protective film extends from a surface of thegate interconnection line through the trench to the surface of the firstmain electrode.

The provision of the surface protective film covering the trenchelectrically isolating the first main electrode and the gateinterconnection line connecting the portions of the gate electrodecorresponding to the plurality of channels from each other in the IGBTconstruction prevents shorting of the gate interconnection line and thefirst main electrode if the trench for electrically isolating the gateinterconnection line and the first main electrode may be long,increasing the product yield of the large-capacitance semiconductordevice of the IGBT construction.

Preferably, the surface protective film is a semi-insulation film havinga conductivity ranging from 1×10⁻¹⁴ to 1×10⁻¹⁰ (1/Ωcm).

Preferably, the surface protective film is a semi-insulation film havinga conductivity ranging from 1×10⁻¹³ to 1×10⁻¹¹ (1/Ωcm).

Since the surface protective film is a semi-insulation film, an electricfield shield effect generated in the surface protective film provides ashield against electrical charges such as externally deposited impurityions to prevent the decrease in breakdown voltage of the semiconductordevice due to external contamination, achieving a high breakdownvoltage. In addition, the degree of freedom of designing thesemiconductor device and the product yield of the semiconductor deviceare increased.

Preferably, the surface protective film is a nitride film.

The surface protective film which is a semi-insulation nitride filmincreases the breakdown voltage characteristic and easily controls theresistance of the surface protective film in fabrication of thesemiconductor device, increasing the product yield of the semiconductordevice.

The present invention is also intended for a method of fabricating asemiconductor device. According to the present invention, the methodcomprises the steps of: forming a first semiconductor layer of a firstconductivity type having first and second major surfaces on a secondsemiconductor layer of a second conductivity type having first andsecond major surfaces such that the second major surface of the firstsemiconductor layer contacts the first major surface of the secondsemiconductor layer, to form a semiconductor body; selectively forming afirst semiconductor region of the second conductivity type in the firstmajor surface of the first semiconductor layer so that the firstsemiconductor layer is exposed in a peripheral portion of the firstmajor surface of the first semiconductor layer and the firstsemiconductor layer is exposed in the form of insular regions in acentral portion of the first major surface of the first semiconductorlayer; forming a second semiconductor region of the first conductivitytype in a surface of the first semiconductor region, with channelregions provided between the second semiconductor region and the insularregions of the first semiconductor layer in the surface of the firstsemiconductor region; forming a gate insulating film on a surface of thechannel regions; forming a gate on the gate insulating film; forming aninterlayer insulating film on a surface of the gate; forming a firstmain electrode covering a surface of the second semiconductor region,with the interlayer insulating film therebetween, and electricallyconnected to the second semiconductor region, the first main electrodebeing formed such that an end of the first main electrode extends to aboundary between the peripheral portion of the first major surface ofthe first semiconductor layer and the central portion thereof;performing radiation for lifetime control; performing heat treatment foreliminating distortion; integrally forming a surface protective film atleast over the peripheral portion of the first major surface of thefirst semiconductor layer other than the central portion thereof afterthe steps of performing radiation and performing heat treatment; andforming a second main electrode on the second major surface of thesecond semiconductor layer.

In the method according to the present invention, the surface protectivefilm is integrally formed at least over the peripheral portion of thefirst major surface of the first semiconductor layer other than thecentral portion of the first main electrode after the high-energyradiation for lifetime control and the heat treatment for distortionelimination. Since the surface protective film is formed after reductionin defects at the silicon-silicon oxide interface generated by theradiation, the amount of hydrogen atoms migrating to the cell area andthe bonds of hydrogen atoms to the dangling bonds are reduced, wherebyan electrically highly reliable semiconductor device is readilyfabricated.

According to another aspect of the present invention, a method offabricating a semiconductor device, comprises the steps of: forming afirst semiconductor layer of a first conductivity type having first andsecond major surfaces on a second semiconductor layer of a secondconductivity type having first and second major surfaces such that thesecond major surface of the first semiconductor layer contacts the firstmajor surface of the second semiconductor layer, to form a semiconductorbody; selectively forming a first semiconductor region of the secondconductivity type in the first major surface of the first semiconductorlayer so that the first semiconductor layer is exposed in a peripheralportion of the first major surface of the first semiconductor layer andthe first semiconductor layer is exposed in the form of insular regionsin a central portion of the first major surface of the firstsemiconductor layer; forming a second semiconductor region of the firstconductivity type in a surface of the first semiconductor region, withchannel regions provided between the second semiconductor region and theinsular regions of the first semiconductor layer in the surface of thefirst semiconductor region; forming a gate insulating film on a surfaceof the channel regions; forming a gate on the gate insulating film;forming an interlayer insulating film on a surface of the gate;selectively forming a gate interconnection line on the surface of thegate; forming a first main electrode having a trench electricallyinsulating the first main electrode and the gate interconnection linefor covering a surface of the second semiconductor region, with theinterlayer insulating film therebetween, and electrically connected tothe second semiconductor region, the first main electrode being formedsuch that an end of the first main electrode extends to a boundarybetween the peripheral portion of the first major surface of the firstsemiconductor layer and the central portion thereof; performingradiation for lifetime control; performing heat treatment foreliminating distortion; integrally forming a surface protective filmover the entire top surface except a part of a surface of the first mainelectrode and a part of a surface of the gate interconnection line; andforming a second main electrode on the second major surface of thesecond semiconductor layer.

In this method according to the present invention, the surfaceprotective film is integrally formed over the surface of the first mainelectrode except the part of the first main electrode and the part ofthe gate interconnection line after the high-energy radiation forlifetime control and the heat treatment for distortion elimination.Since the surface protective film is formed after reduction in defectsat the silicon-silicon oxide interface generated by the radiation, thebonds of hydrogen atoms to the dangling bonds are reduced, with theconventional structure, whereby an electrically highly reliablesemiconductor device is readily fabricated.

According to still another aspect of the present invention, a method offabricating a semiconductor device, comprises the steps of: forming afirst semiconductor layer of a first conductivity type having first andsecond major surfaces on a second semiconductor layer of a secondconductivity type having first and second major surfaces such that thesecond major surface of the first semiconductor layer contacts the firstmajor surface of the second semiconductor layer, to form a semiconductorbody; selectively forming a first semiconductor region of the secondconductivity type in the first major surface of the first semiconductorlayer so that the first semiconductor layer is exposed in a peripheralportion of the first major surface of the first semiconductor layer andthe first semiconductor layer is exposed in the form of insular regionsin a central portion of the first major surface of the firstsemiconductor layer; forming a second semiconductor region of the firstconductivity type in a surface of the first semiconductor region, withchannel regions provided between the second semiconductor region and theinsular regions of the first semiconductor layer in the surface of thefirst semiconductor region; forming a gate insulating film on a surfaceof the channel regions; forming a gate on the gate insulating film;forming an interlayer insulating film on a surface of the gate;selectively forming a gate interconnection line on the surface of thegate; forming a first main electrode having a trench electricallyinsulating the first main electrode and the gate interconnection linefor covering a surface of the second semiconductor region, with theinterlayer insulating film therebetween, and electrically connected tothe second semiconductor region, the first main electrode being formedsuch that an end of the first main electrode extends to a boundarybetween the peripheral portion of the first major surface of the firstsemiconductor layer and the central portion thereof; performingradiation for lifetime control; performing heat treatment foreliminating distortion; integrally forming a surface protective film atleast over the peripheral portion of the first major surface of thefirst semiconductor layer and extending from a surface of the gateinterconnection line through the trench to a surface of the first mainelectrode after the steps of performing radiation and performing heattreatment; and forming a second main electrode on the second majorsurface of the second semiconductor layer.

In this method according to the present invention, the surfaceprotective film is integrally formed over the peripheral portion of thefirst main electrode and extending from the surface of the gateinterconnection line through the trench to the surface of the first mainelectrode after the high-energy radiation for lifetime control and theheat treatment for distortion elimination. Since the surface protectivefilm is formed after reduction in defects at the silicon-silicon oxideinterface generated by the radiation, the amount of hydrogen atomsmigrating to the cell area and the bonds of hydrogen atoms to thedangling bonds are reduced, whereby an electrically highly reliablesemiconductor device is readily fabricated.

It is an object of the present invention to provide a semiconductordevice having an MOS gate for reducing variations in threshold voltageV_(th) with time to stabilize electrical characteristics thereof, and amethod of fabricating the same.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmentary plan view of a power IGBT according to a firstpreferred embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view taken along the line II—IIof FIG. 1;

FIG. 3 is a fragmentary plan view taken along the line III—III of FIG. 2at the surface of a semiconductor body;

FIG. 4 is a fragmentary plan view illustrating a plan configuration of agate electrode of FIG. 1;

FIG. 5 is a flow chart of fabrication process of the semiconductordevice according to the present invention;

FIGS. 6 to 12 are cross-sectional views illustrating the fabricationprocess of the semiconductor device according to the present invention;

FIG. 13 is a cross-sectional view of a test piece for use in a C-V test;

FIG. 14 is a graph illustrating ΔV_(FB) (normalization value) for theC-V test;

FIG. 15 is a graph illustrating a breakdown voltage characteristic yieldof the semiconductor device according to the present invention;

FIG. 16 is a fragmentary plan view of the semiconductor device accordingto a second preferred embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view taken along the lineXVII—XVII of FIG. 16;

FIG. 18 is a graph for comparison between a threshold voltage V_(th)variation percentage of the present invention and a threshold voltageV_(th) variation percentage of the background art;

FIG. 19 is a fragmentary plan view of a conventional semiconductordevice;

FIG. 20 is a cross-sectional view taken along the line XX—XX of FIG. 19;

FIG. 21 is a flow chart of fabrication process of the conventionalsemiconductor device; and

FIG. 22 is a graph of an HTGB test result for the conventionalsemiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

FIG. 1 is a fragmentary plan view of a power IGBT according to a firstpreferred embodiment of the present invention. FIG. 2 is a fragmentarycross-sectional view taken along the line II—II of FIG. 1. FIG. 3 is afragmentary plan view taken along the line III—III of FIG. 2 at thesurface of a semiconductor body. FIG. 4 is a fragmentary plan viewillustrating a plan configuration of a gate electrode shown in FIG. 1.In the fragmentary plan view of the gate electrode in FIG. 4, only thegate electrode and portions formed simultaneously with the gateelectrode are illustrated and other portions are not illustrated.

In FIGS. 1 and 2, the reference numeral 1 designates a P⁺ substrateserving as a second semiconductor layer; 2 designates an N⁺ layer; 3designates an N⁻ layer. The N⁺ layer 2 and the N⁻ layer 3 form a firstsemiconductor layer. The reference numeral 4 designates a semiconductorbody comprised of the P⁺ substrate 1, the N⁺ layer and the N⁻ layer 3; 5designates a P⁺ base layer serving as a first semiconductor region; 6designates an N⁺ emitter layer serving as a second semiconductor region;7 designates a gate insulating film of silicon oxide; 8 designates agate electrode of polysilicon serving as a gate; 9 designates a gateinterconnection line of Al; 10 designates an emitter electrode of Alserving as a first main electrode; 11 designates guard rings which areP⁺ diffusion regions; 12 designates a passivation film of PSG serving asan interlayer insulating film for isolation between the gate electrode 8and the emitter electrode 10; 14 designates a surface protective filmwhich is a semi-insulation film of silicon nitride for covering aperipheral area surface of the IGBT; 15 designates a channel stopper; 16designates and 161 designate a silicon oxide film; 17 designates apolysilicon film; 18 designates a passivation film; and 19 designates acollector electrode serving as a second main electrode.

Referring to FIG. 3, the N⁻ layer 3 is exposed in the form of insularregions on the surface of a central portion of the device, and the P⁺base layer 5 covers the surface except the insular regions of the N⁻layer 3. The N⁺ emitter layer 6 is formed in the P⁺ base layer 5, withnarrow portions of the P⁺ base layer 5 sandwiched between the N⁺ emitterlayer 6 and the insular regions of the N⁻ layer 3. The narrow portionsof the P⁺ base layer 5 between the insular regions of the N⁻ layer 3 andthe N⁺ emitter layer 6 serve as channel regions. The gate insulatingfilm 7 on the surface of the channel region is formed integrally overthe plurality of channel regions. The integral gate electrode 8 ofsubstantially the same configuration as the gate insulating film 7 isformed on the surface of the integral gate insulating film 7, as shownin FIG. 4.

As the number of channels opposed to the gate electrode 8 increases,gate potentials opposed to the respective channels are not necessarilyuniform in the gate electrode 8. To provide uniform gate potentials, thegate interconnection line 9 of aluminum is provided to connect theportions of the gate electrode 8 opposed to the respective channels(FIGS. 1 and 2). The gate interconnection line 9 extends to the centerof the device and is connected to a gate bonding pad (not shown) in thecenter of the device. Connection lines to the exterior are bonded to thegate bonding pad. An area in which the gate interconnection line 9 andthe bonding pad are provided is a gate wiring area 32.

The emitter electrode 10 is formed on the surface of the gate electrode8 except the portion where the gate interconnection line 9 is formed,with the passivation film 12 formed therebetween. The emitter electrode10 short-circuits the P⁺ base layer 5 and the N⁺ emitter layer 6 on thesurface of the semiconductor body 4 and is electrically isolated fromthe gate interconnection line 9 by a trench. An area in which theemitter electrode 10 is formed is a cell area 31 (FIGS. 1 and 2).

The N⁻ layer 3 is exposed in a peripheral portion surrounding thesurface of the semiconductor body 4. The peripheral portion generallycorresponds to a device peripheral area 30 on the surface of thesemiconductor body 4 other than the gate wiring area 32 and the cellarea 31.

The plurality of annular guard rings 11 are formed in the N⁻ layer 3 inthe peripheral portion to surround the outer periphery of the cell area31. The channel stopper 15 which is an N⁺ diffusion region is formed onthe outermost edge of the N⁻ layer 3 in the peripheral portion tosurround the guard rings 11. The inner periphery of the channel stopper15 is adapted such that the channel stopper 15 are generally equallyspaced from the outermost guard ring 11 over the entire circumference.The surface protective film 14 which is a semi-insulation film ofsilicon nitride directly covers the surface of the channel stopper 15,and covers the surfaces of the N⁻ layer 3 in the peripheral portion andthe outer peripheral portion of the P⁺ base layer 5, with the siliconoxide film 16 and passivation film 18 formed therebetween. The surfaceprotective film 14 is integrally formed such that an inner peripheralend thereof overlapping and covering the outer peripheral portion of theemitter electrode 10 and an outer peripheral end thereof extends to theouter end of the channel stopper 15 to prevent the surface of thepassivation film 18 from being exposed. An area in which the surfaceprotective film 14 is formed is the device peripheral area 30.

An MOSFET is similar in construction to the IGBT except that the MOSFETdoes not include the P⁺ substrate 1 of the IGBT. That is, the MOSFET isconstructed such that the P⁺ substrate 1 of the IGBT is removed and theN⁺ layer 2 of the IGBT is replaced with an N⁺ substrate on which a drainelectrode is formed.

A method of fabricating a semiconductor device will now be describedhereinafter.

FIG. 5 is a flow chart of the fabrication process of an IGBT as anexample of the semiconductor device of the present invention. FIGS. 6 to12 are cross-sectional views illustrating the fabrication process of theIGBT.

Referring to FIG. 5 and FIGS. 6 to 12, the N⁺ layer 2 and the N⁻ layer 3are formed on the P⁺ substrate 1 in this order by the epitaxial growthtechnique to form the semiconductor body 4 (FIG. 6). When the N⁺ layer 2and the N⁻ layer 3 are thicker than the P⁺ substrate 1, a P⁺ layer maybe formed on an N substrate by the epitaxial growth technique.Otherwise, a P⁺ layer and an N layer joined together may be formed on aP or N substrate by diffusion.

The silicon oxide film 16 is formed on the surface of the semiconductorbody 4 and is then etched by photolithography, and the P wells and theP⁺ base layer 5 are formed by diffusion (FIG. 7).

The oxide film 16 is then etched, if necessary, after photolithographyprocess, and the gate insulating film 7 and silicon oxide film 161 ofsilicon oxide is are formed by thermal oxidation. The gate electrode 8of polysilicon is formed on the surface of the gate insulating film 7after photolithography process (FIG. 8).

Photolithography process and thermal diffusion process are performed toform the N⁺ emitter layer 6 in the P⁺ base region 5 and the channelstopper 15 in the peripheral portion surface of the N⁻ layer 3 (FIG. 9).

The passivation films 15 12 and 18 of PSG are formed on the top surface,and electrode contact portions are etched (FIG. 10).

The gate interconnection line 9 and the emitter electrode 10 are formedby Al—Si sputtering (FIG. 11).

For the IGBT, radiation for lifetime control and heat treatment forelimination of distortion generated in portions subjected to theradiation are performed, and the surface protective film 14 is formed onthe device top surface. The order of the process steps is the feature ofthe method of fabricating the IGBT according to the present invention.

Specifically, according to the present invention, the radiation forlifetime control is performed first. Then the heat treatment isperformed to eliminate the distortion generated in the portionssubjected to the radiation. Finally, the surface protective film 14 isformed on the top surface of the device.

The heat treatment for distortion elimination is performed, for example,at a temperature of about 300 to 400° C. The final P-CVD process in anatmosphere of a mixed silane-ammonia gas is performed at a temperatureslightly lower than the heat treatment temperature for distortionelimination. The film may be formed at a temperature of about 300° C.with the current state of the art.

To form the surface protective film 14, a semi-insulation siliconnitride film is formed over the device surface by the P-CVD process, anda mask is formed by photolithography, and then plasma etching isperformed in an atmosphere of CF₄ and O₂ to remove the silicon nitridefilm in the cell area 31 centrally of the device and in the gate wiringarea 32 is removed, with the silicon nitride film left only in thedevice peripheral area 30. This completes the fabrication process (FIG.12).

In the above described method, the radiation for lifetime control, theheat treatment for distortion elimination, and the step of leaving thesilicon nitride film only in the device peripheral area 30 by the P-CVDprocess are carried out in this order. Only the arrangement in which thesilicon nitride film is left only in the device peripheral area 30 canconsiderably reduce the variations in threshold voltage V_(th). Thus,the above-described process may be replaced with a process of formingthe electrode by Al—Si sputtering (FIG. 11), forming the semi-insulationsilicon nitride film only in the device peripheral area 30 by the P-CVDprocess, performing the radiation for lifetime control, and thenperforming the heat treatment for distortion elimination.

Such a method can provide an electrically highly stable IGBT with asatisfactory breakdown voltage characteristic by using a conventionalfabrication line without a new fabrication line.

A method of fabricating an MOSFET is similar to the method offabricating the IGBT except that the radiation for lifetime control andthe heat treatment for distortion elimination are not performed.

Operation will be described below.

The above stated IGBT according to the present invention includes thesemi-insulation silicon nitride film formed by the P-CVD process only inthe device peripheral area 30 other than the gate wiring area 32 andcell area 31. Hydrogen atoms to be bonded to dangling bonds at thesilicon-silicon oxide interface are contained only in the siliconnitride film in the device peripheral area 30. The hydrogen atoms, ifmoved, migrate to the silicon-silicon oxide interface under the surfaceprotective film 14, and fewer hydrogen atoms migrate up to the cell area31. This decreases the number of hydrogen atoms bonded to the danglingbonds at the silicon-silicon oxide interface in the channel regionsunder the gate electrode 8 in the cell area 31 and, accordingly, reducesthe number of Si—H chemical bonds generated at the silicon-silicon oxideinterface, to prevent an unstable interface state. Therefore, thephenomenon in which the threshold voltage V_(th) varies over a long timeperiod and requires long time to be saturated is difficult to occur.

Operation of the MOSFET is similar to that of the IGBT when the siliconnitride film is formed only in the device peripheral area 30.

For the IGBT, the radiation for lifetime control and the heat treatmentfor distortion elimination are essential. If the formation of thesilicon nitride film by the P-CVD process after the two process stepsincreases the number of defects at the silicon-silicon oxide interfacedue to the radiation to increase the dangling bonds, the subsequent heattreatment reduces the number of defects at the silicon-silicon oxideinterface to reduce the number of dangling bonds and, accordingly, thenumber of Si—H chemical bonds generated at the silicon-silicon oxideinterface, preventing the unstable interface state. The influence of theradiation is eliminated, and the acceleration of the V_(th) variationsdue to the radiation is difficult to occur.

The use of the semi-insulation silicon nitride film as the surfaceprotective film 14 causes a slight current to flow between the emitterand channel stopper to produce an electric field shield effect in thedevice peripheral area 30. This provides a shield against externalimpurity ions, to improve the breakdown voltage characteristic of thedevice. For example, an IGBT having a breakdown voltage as high as 1700V requires the electric field shield effect using the semi-insulationsilicon nitride film.

To simply examine the evaluation of the V_(th) variations for an MISstructure (metal insulator semiconductor structure) as the premise ofthe present invention, a C-V test (capacitance-voltage test) wasperformed under various conditions.

FIG. 13 is a cross-sectional view of a test piece used for the C-V test.

In FIG. 13, the reference numeral 40 designates a surface protectivefilm; 41 designates an aluminum electrode; 42 designates a thermaloxidation film; 43 designates an N-type silicon layer; and 44 designatesa capacitance measuring device.

The C-V test employs the test piece as above described for measuring avoltage and capacitance between the aluminum electrode 41 and the N-typesilicon layer 43, with the voltage varied, to determine a flat-bandvoltage V_(FB) between the thermal oxidation film 42 and the N-typesilicon layer 43. There is a correlation between the flat-band voltageV_(FB) and the threshold voltage V_(th). The value of variation ΔV_(FB)of the flat-band voltage V_(FB) is determined under various conditionssuch as the presence/absence of the surface protective film 40 of thetest piece and processing conditions. On the basis of the value ΔV_(FB)is evaluated and examined the value of variation ΔV_(th) of thethreshold voltage V_(th) of the surface protective film 14 of a devicehaving an MOS gate.

As the test piece for the C-V test was used a (100) crystal planeoriented N-type silicon on which was formed a silicon thermal oxidationfilm of about 1000 Å in thickness, with aluminum sputtered on thesurface thereof for use as an electrode. After the aluminum electrode 41was formed, the surface protective film 40 was formed. A P-CVD nitridefilm containing a large amount of hydrogen atoms and an LP-CVD oxidefilm containing a small amount of hydrogen atoms were selected as thesurface protective film 40. For hydrogen sintering, heat treatment wasperformed in a high-temperature furnace in an atmosphere of hydrogen ata temperature of 400° C. for 30 minutes. The radiation is an electronbeam irradiation which is a conventional IGBT carrier lifetime controlprocess, followed by heat treatment for distortion elimination.

TABLE 1 ΔV_(th) radiation (normal- hydrogen & heat ization judge- spec.protective film sintering treatment value) ment A no film not done notdone 0.10 ∘ B LP-CVD oxide film not done not done 0.10 ∘ C P-CVD nitridefilm not done not done 0.50 Δ D no film done not done 0.45 Δ E LP-CVDoxide film not done done 0.10 ∘ F P-CVD nitride film not done done 1.00x G no film done done 0.90 x H hydrogen sintering after 0.10 ∘ radiation& heat treatment

Table 1 illustrates the conditions and results of the C-V test.

Additional explanation of Table 1 will be described below.

-   -   (1) To determine the value of variation ΔV_(th), the flat-band        voltage V_(FB) was first determined, and then the test piece was        held at 150° C., and a 30 V d.c. bias voltage was applied for 5        minutes, with the aluminum electrode 41 being negative. The        flat-band voltage V_(FB) was measured again to calculate the        difference ΔV_(FB) between the first and second V_(FB)        measurements.    -   (2) The LP-CVD oxide film in spec. B was a PSG film formed by        the LP-CVD process.    -   (3) The P-CVD nitride film in spec. C was a semi-insulation film        containing a large amount of silicon.    -   (4) The radiation and heat treatment were performed after the        protective film was formed in specs. E and F.    -   (5) The radiation and heat treatment were performed after the        hydrogen sintering in spec. G.    -   (6) No protective film was formed in spec. H.    -   (7) ΔV_(FB) (normalization value) was a ratio of ΔV_(FB) in each        spec. to ΔV_(FB) in spec. F.

FIG. 14 is a graph illustrating ΔV_(FB) (normalization value) for theC-V test of Table 1.

Referring to FIG. 14, ΔV_(FB) (normalization value) is low in specs. A,B and E with few hydrogen atoms and is high in specs. C and D with alarge amount of hydrogen atoms. The radiation after the formation of theprotective film further increases ΔV_(FB) (normalization value). It willbe apparent from the graph of FIG. 14 that:

-   -   (1) V_(FB) is varied by introduction of hydrogen atoms into the        MIS structure (specs. C and D),    -   (2) V_(FB) is varied more widely by the radiation in addition to        the introduction of hydrogen atoms (specs. F and G),    -   (3) V_(FB) is not varied by the radiation only (spec. E), and    -   (4) V_(FB) is not varied by the introduction of hydrogen atoms        after the radiation and the heat treatment (spec. H).

Therefore, it will be understood that:

-   -   (i) it is necessary to prevent hydrogen atoms from entering the        cell area 31 having the channels in the MIS structure or the        device having the MOS gate,    -   (ii) it is also necessary to prevent hydrogen atoms from        entering the cell area 31, particularly in the IGBT performing        lifetime control, and    -   (iii) the introduction of hydrogen atoms after the radiation and        heat treatment exerts no influence on the V_(FB) variations in        the IGBT performing lifetime control. An electrically highly        stable IGBT with a satisfactory breakdown voltage characteristic        is accomplished by the provision of the surface protective film        14 which is the semi-insulation silicon nitride film formed by        the P-CVD process only in the device peripheral area 30 like the        first preferred embodiment and by the process steps of        performing radiation for lifetime control, performing heat        treatment for distortion elimination, and then forming the        surface protective film 14 on the device top surface.

An electrically highly stable MOSFET with a satisfactory breakdownvoltage characteristic is accomplished by the provision of the surfaceprotective film 14 which is the semi-insulation silicon nitride filmformed by the P-CVD process only in the device peripheral area 30 otherthan the gate wiring area 32 and the cell area 31.

FIG. 15 is a graph illustrating a breakdown voltage characteristic yieldof the structure of the first preferred embodiment.

Referring to FIG. 15, the guard ring structure A includes eight guardrings 11 surrounding the outer periphery of the cell area 31, and theguard ring structure B includes ten guard rings 11 such that a distancebetween the outermost guard ring 11 and the channel stopper 15 is 1.3times the distance therebetween of the guard ring structure A.

It will be appreciated from the graph of FIG. 15 that there is adifference in breakdown voltage characteristic yield between the guardring structure A and the guard ring structure B when the conductivity ofthe surface protective film 14 is less than 1×10⁻¹³/Ωcm, but there is nodifference in breakdown voltage characteristic yield therebetween withthe increasing breakdown voltage characteristic yield when theconductivity is not less than 1×10⁻¹³/Ωcm. This indicates not only theimprovement in breakdown voltage characteristic by the electric fieldshield effect but also that the device breakdown voltage characteristicis stabilized by the use of the semi-insulation surface protective film14 with the conductivity of not less than 1×10⁻¹³ /Ωcm. This increasesthe degree of freedom to determine the guard ring structure dimensionand the degree of freedom of design, for example, the stable breakdownvoltage characteristic independent of variations in fabrication processof the guard ring structure. However, an excessively high conductivityeliminates the function of the insulating film. Thus, the conductivityof the surface protective film 14 is required to be on the order of1×10⁻¹⁴ to 1×10⁻¹⁰ (1/Ωcm) and is preferably 1×10⁻¹³ to 1×10⁻¹¹ (1/Ωcm)which permits easy control of the conductivity of the semi-insulationsilicon nitride film by measuring the refractive index of the film.

Second Preferred Embodiment

FIG. 16 is a fragmentary plan view of the IGBT according to a secondpreferred embodiment of the present invention. FIG. 17 is a fragmentarycross-sectional view taken along the line XVII—XVII of FIG. 16.

Referring to FIGS. 16 and 17, the IGBT comprises the surface protectivefilm 14 formed in the gate wiring area 32 and the device peripheral area30.

The emitter electrode 10 is electrically isolated from the gateinterconnection line 9 by a narrow trench. The emitter electrode 10 andthe gate interconnection line 9 which are Al—Si sputtering film areeasily scratched, for example, when the semiconductor device is handledby a handling device during the fabrication process, resulting inshorting of the emitter electrode 10 and the gate interconnection line9. However, such a failure is prevented by the surface protective film14 extending to the surface of the narrow trench. In addition, sincethere is no channel regions serving as cells under the gate wiring area32, the covering of the semi-insulation surface protective film 14 ofsilicon nitride formed by the P-CVD process and containing a largeamount of hydrogen atoms does not cause the V_(th) variations.Therefore, an electrically highly stable IGBT is accomplished, withshorting of the emitter electrode 10 and the gate interconnection line 9being prevented, like the first preferred embodiment.

Further, an electrically highly stable MOSFET is accomplished, withshorting of the emitter electrode 10 and the gate interconnection line 9being prevented, like the first preferred embodiment by the provision ofthe surface protective film 14 in the gate wiring area 32 and the deviceperipheral area 30 of the MOSFET.

Third Preferred Embodiment

The third preferred embodiment according to the present inventionincludes an IGBT device structure identical with the conventionalstructure of FIG. 19 but fabricated by the process corresponding to thatof FIG. 5 and FIGS. 6 to 12.

Specifically, the third preferred embodiment is similar to the firstpreferred embodiment in the process steps between the formation of thesemiconductor body 4 (FIG. 6) and the electrode formation by Al—Sisputtering (FIG. 11). Then radiation is performed for lifetime control,and heat treatment is performed to eliminate distortion, and the surfaceprotective film 14 is finally formed on the device top surface.

The surface protective film 14 on the device top surface is asemi-insulation silicon nitride film formed by the P-CVD process tocover the IGBT surface except the emitter wire bonding region 13, thegate interconnection line, and the gate bonding pad which is a part ofthe gate interconnection line.

As concluded from the C-V test result that (iii) the introduction ofhydrogen atoms is permitted after the radiation for lifetime control andheat treatment for distortion elimination in the IGBT performinglifetime control, the use of the fabrication method of the thirdpreferred embodiment allows defects generated due to the radiation to bereduced by the heat treatment to reduce the number of dangling bonds atthe silicon-silicon oxide interface. The Si—H chemical bonds becomesdifficult to generate at the silicon-silicon oxide interface.

For this reason, if the P-CVD nitride film containing a large amount ofhydrogen atoms is provided in the cell area 31, the number of Si—Hchemical bonds is reduced at the silicon-silicon oxide interface in thecell area 31, providing a stable interface state. Thus, there isprovided an electrically highly stable IGBT of the conventionalconstruction with a small amount of long-term V_(th) variations, whereinshorting of the emitter electrode 10 and gate interconnection line 9 isprevented, like the first preferred embodiment.

FIG. 18 is a graph for comparison of the percentage of variations inthreshold voltage V_(th) between the present invention and thebackground art.

Referring to FIG. 18, the percentage of variations in threshold voltageafter a reverse bias test is a little over 15% and a little over 10% forthe IGBT of the conventional construction having the protective filmcovering 90% and 70% of the cell area, respectively. The percentage ofvariations in threshold voltage after the reverse bias test is about 2%for the IGBT of the first preferred embodiment of the present inventionhaving the protective film covering 0% of the cell area, and thepercentage is about 2% for the IGBT of the second preferred embodimentof the present invention having the protective film covering 10% of thecell area. The first and second preferred embodiments provide thepercentage generally equal to the percentage of variations in thresholdvoltage for the conventional IGBT having the PSG film containing a smallamount of hydrogen atoms and formed by the LP-CVD process. For the IGBTof the third preferred embodiment having the protective film covering75% of the cell area and fabricated by the process of performingradiation, performing heat treatment for distortion elimination, andthen forming the silicon nitride surface protective film by the P-CVDprocess, the percentage of variations in threshold voltage is a littlehigher than but generally equal to the percentages of the first andsecond preferred embodiments.

In this manner, the first, second and third preferred embodimentsachieve the electrically highly stable semiconductor device with the MOSgate having a satisfactory breakdown voltage characteristic.

The above-mentioned preferred embodiments describe the powersemiconductor device having the MOS gate. However, the present inventionis also applicable to semiconductor integrated circuit devices, such asmemories, having an MOS gate.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1. A semiconductor device comprising: a first semiconductor layer havinga first doping state of a first conductivity type and having first andsecond major surfaces; a first semiconductor region of a secondconductivity type formed selectively in said first major surface of saidfirst semiconductor layer so that said first semiconductor layer isexposed in remains in the first doping state along a peripheral portionof said first major surface, and said first semiconductor layer isexposed in remains in the first doping state in the a form of an insularregion in a planar view in a central portion of said first majorsurface; a second semiconductor region of the first conductivity typeformed in a surface of said first semiconductor region, with a channelregion provided between said second semiconductor region and saidinsular region of said first semiconductor layer; a gate insulating filmformed on a surface of said channel region; a first gate electrode froma plurality of gate electrodes formed on said gate insulating film; aninterlayer insulating film formed at least on said first gate electrode;a first main electrode formed over a surface of said interlayerinsulating film and covering a surface of said second semiconductorregion, said first main electrode being electrically connected to saidsecond semiconductor region and having an end extending to a boundarybetween the peripheral portion of said first major surface and thecentral portion of said first major surface; a second main electrodeformed on said second major surface of said first semiconductor layer;and an integral semi-insulating plasma CVD nitride film covering atleast the peripheral portion of said first major surface other than thecentral portion of said first major surface and not extending to anupper portion of said first gate above any gate electrode, said integralsemi-insulating plasma CVD nitride film having a conductivity which doesnot lose function as an insulating film and stabilizes breakdown voltagecharacteristics of the semiconductor device.
 2. The semiconductor deviceof claim 1, wherein said plasma CVD nitride film extends from theperipheral portion of said first major surface to a surface of saidfirst main electrode at said end.
 3. The semiconductor device of claim1, further comprising: a second gate electrode from the plurality ofgate electrodes not covered with said first gate main electrode; and agate interconnection line formed selectively on a surface of said secondgate electrode, wherein a trench is formed between said first mainelectrode and said gate interconnection line for electrical isolationbetween said first main electrode and said gate interconnect line, andwherein said first gate electrode and said second gate electrode areintegrally formed and electrically connected by said gateinterconnection line to each other.
 4. The semiconductor device of claim3, wherein said plasma CVD nitride film further extends from a surfaceof said gate interconnection line through said trench to a portion of asurface of said first main electrode.
 5. The semiconductor device ofclaim 4, wherein said plasma CVD nitride film is a semi-insulation filmhaving a conductivity ranging from 1×10⁻¹⁴ to 1×10⁻¹⁰ (1/Ωcm).
 6. Thesemiconductor device of claim 4, wherein said plasma CVD nitride film isa semi-insulation film having a conductivity ranging from 1×10⁻¹³ to1×10⁻¹¹ (1/Ωcm).
 7. The semiconductor device of claim 1, furthercomprising: a second semiconductor layer of the second conductivity typeformed between said second major surface of said first semiconductorlayer and said second main electrode.
 8. The semiconductor device ofclaim 7, further comprising: a second gate electrode from the pluralityof gate electrodes not covered with said first main electrode; and agate interconnection line formed selectively on a surface of said secondgate electrode, wherein a trench is formed between said first mainelectrode and said gate interconnection line for electrical isolationbetween said first main electrode and said gate interconnect line, andwherein said first gate electrode and said second gate electrode areintegrally formed and electrically connected by said gateinterconnection line to each other.
 9. The semiconductor device of claim8, wherein said surface protective film plasma CVD nitride film furtherextends from a surface of said gate interconnection line through saidtrench to a portion of a surface of said first main electrode.
 10. Thesemiconductor device of claim 9, wherein said plasma CVD nitride film isa semi-insulation film having a conductivity ranging from 1×10⁻¹⁴ to1×10⁻¹⁰ (1/Ωcm).
 11. The semiconductor device of claim 9, wherein saidplasma CVD nitride film is a semi-insulation film having a conductivityranging from 1×10⁻¹³ to 1×10⁻¹¹ (1/Ωcm).
 12. A semiconductor devicecomprising: a first semiconductor layer having a first doping state of afirst conductivity type and having first and second major surfaces; atleast one first semiconductor region of a second conductivity typeformed selectively in said first major surface of said firstsemiconductor layer so that said first semiconductor layer is exposed inremains in the first doping state along a peripheral portion of saidfirst major surface, and said first semiconductor layer is exposed inregion remains in the first doping state in the a form of a plurality ofinsular regions in a planar view in a central portion of said firstmajor surface; a plurality of second semiconductor regions of the firstconductivity type formed in a surface of said at least one firstsemiconductor region, with channel regions provided between said secondsemiconductor regions and said insular regions of said firstsemiconductor layer; a gate insulating film formed on a surface of saidchannel regions; a first gate electrode from a plurality of gateelectrodes formed on said gate insulating film; an interlayer insulatingfilm formed at least on said first gate electrode; a first mainelectrode formed over a surface of said interlayer insulating film andcovering a surface of said second semiconductor region, said first mainelectrode being electrically connected to said plurality of secondsemiconductor regions, said first main electrode further having an endextending to a boundary between the peripheral portion of said firstmajor surface and the central portion of said first major surface; asecond main electrode formed on said second major surface of said firstsemiconductor layer; and an integral semi-insulating plasma CVD nitridefilm for covering at least the peripheral portion of said first majorsurface other than the central portion of said first major surface andnot extending to an upper portion of said first gate above any gateelectrode, said integral semi-insulating plasma CVD nitride film havinga conductivity which does not lose function as an insulating film andstabilizes breakdown voltage characteristics of the semiconductordevice.
 13. The semiconductor device of claim 12, wherein said plasmaCVD nitride film extends from the peripheral portion of said first majorsurface to a surface of said first main electrode at said end.
 14. Thesemiconductor device of claim 13, further comprising: a second gateelectrode from the plurality of gate electrodes not covered with saidfirst main electrode; and a gate interconnection line formed selectivelyon a surface of said second gate electrode, wherein a trench is formedbetween said first main electrode and said gate interconnection line forelectrical isolation between said first main electrode and said gateinterconnect line, and wherein said first gate electrode and said secondgate electrode are integrally formed and electrically connected by saidgate interconnection line to each other.
 15. The semiconductor device ofclaim 14, wherein said plasma CVD nitride film further extends from asurface of said gate interconnection line through said trench to aportion of a surface of said first main electrode.
 16. The semiconductordevice of claim 15, wherein said plasma CVD nitride film is asemi-insulation film having a conductivity ranging from 1×10⁻¹⁴ to1×10⁻¹⁰ (1/Ωcm).
 17. The semiconductor device of claim 15, wherein saidplasma CVD nitride film is a semi-insulation film having a conductivityranging from 1×10⁻¹³ to 1×10⁻¹¹ (1/Ωcm).
 18. The semiconductor device ofclaim 13, further comprising: a second semiconductor layer of the secondconductivity type formed between said second major surface of said firstsemiconductor layer and said second main electrode.
 19. Thesemiconductor device of claim 18, further comprising: a second gateelectrode from the plurality of gate electrodes not covered with saidfirst main electrode; and a gate interconnection line formed selectivelyon a surface of said second gate electrode, wherein a trench is formedbetween said first main electrode and said gate interconnection line forelectrical isolation between said first main electrode and said gateinterconnect line, and wherein said first gate electrode and said secondgate electrode are integrally formed and electrically connected by saidgate interconnection line to each other.
 20. The semiconductor device ofclaim 19, wherein said plasma CVD nitride film further extends from asurface of said gate interconnection line through said trench to aportion of a surface of said first main electrode.
 21. The semiconductordevice of claim 20, wherein said plasma CVD nitride film is asemi-insulation film having a conductivity ranging from 1×10⁻¹⁴ to1×10⁻¹⁰ (1/Ωcm).
 22. The semiconductor device of claim 20, wherein saidplasma CVD nitride film is a semi-insulation film having a conductivityranging from 1×10⁻¹³ to 1×10⁻¹¹ (1/Ωcm).